Electronic adder



Y INVENTOR. BYRON L. HA VEA/5 A TTOR/VEV States ELECTRNIC ADDER Byron L.Havens, Closter, NJ., assgnor to International Business MachinesCorporation, New York, N.Y., a corporation of New York nite 24 Claims.(Cl. 23S-176) This application is a continuation of application SerialNo. 262,731 tiled December 2l, 1951, now abandoned, which is a divisionof application Serial No. 47,626 tiled September 3, 1948, now Patent2,672,283 issued March 16, 1954, which invention relates to a computingdevice and more particularly to a device for computing the product oftwo quantities. The present invention is concerned with adding circuitswhich are of particular utility in connection with devices for computingthe product of two quantities.

A principal object of the present invention is the`provision of improvedadding circuits especially adapted for, but not limited to, use in anelectronic multiplier of the type disclosed and claimed in theabove-mentioned parent patent.

Another object is to provide a novel electronic circuit arrangement foradding two binary numbers supplied thereto in time-coded impulse form.

A further object of the present invention is the provision of a novelcoincidence circuit arrangement which is especially adapted for use inbinary adders.

Still another object is to provide a novel adding circuit which achievesa column shift of one column of the sum and hence is especially adaptedfor use in a chain for adding a plurality of partial products in anelectronic multiplier.

An additional object of the present invention is the provision, in abinary adder, of means for producing a predetermined delay between theinput and output pulses.

The relation of the adding circuits of the present invention to theelectronic multiplier disclosed and claimed in the above-mentionedparent patent will be apparent from the following brief summary. One ofthe two quantities to be multiplied, that is the multiplicand, istranslated into time coded, voltage impulse form and suppliedsimultaneously to a plurality of coincidence circuits corresponding tothe different digital positions in the multiplier, each coincidencecircuit being responsive to the digit in the multiplier in thecorresponding digital position. Then, through the action of thecoincidence circuits, all of the digits of the multiplicand aremultiplied by each digit of the multiplier individually with eachresulting partial product appearing in coded impulse form in the outputof the corresponding coincidence circuit, each digit of the multiplicandbeing simultaneously and individually multiplied by every digit of themultiplier. The partial products thus obtained are then applied to aseries chain of adding circuits, known as adding boxes, at differentpoints on the chain corresponding to the proper columnar position of thepartial products for adding. The resulting sum represents the product ofthe multi-l plicand and the multiplier in time coded impulse form whichmay be translated into another form for recording purposes.

In the time code contemplated for use in connection with the presentinvention, a particular period of time is assigned to each digitalposition in the binary number arent time.

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to be represented. The time base necessary in setting up Ithe code isestablished by the starting impulse from the synchronizer which, in theparticular device illustrated, is repeated at periodic intervals. Thetime immediately following a starting impulse includes a plurality oftime periods of equal length, each time period corresponding to adigital position in the binary number. The first time period following astarting impulse corresponds to the lirst digital position from theright end of the binary number; the second time period corresponds t0the second digital position from the right end of the number; and so onthrough all of the time periods. If a voltage impulse occurs in any timeperiod it represents a binary l at the corresponding digital position inthe binary number. A binary 0 at any digital position is represented bythe absence of a voltage impulse in the corresponding time period.

Other objects and novel features of the invention are pointed out in thefollowing description and claims and illustrated in the accompanyingdrawings, which disclose, by way of example, the principle of theinvention and the best mode, which has been contemplated, of applyingthat principle.

The single figure of the drawing is a detailed circuit diagram of anindividual adding box in accordance with the present invention.

The adding box is provided with three input terminals 222, 223 and 224and two output terminals 225 and 226, one of the latter being a carryoutput terminal 225 which is connected externally to the third inputterminal 224. The first input terminal 222 is to be connected to thecorresponding coincidence circuit through one of lines 221ab (1 8) inFigs. 2h and 2j of the above-identied parent application. The secondinput terminal 223 is t0 be connected to the output terminal 226 of thepreceding adding box in the chain (if present). The output terminal 226is to deliver the sum of the two numbers added.

Inasmuch as the two binary numbers to be supplied to an adding box inaccordance with the present invention are in time coded impulse form, itis evident that only one digit of each number can be supplied to theadding box at any instant. Addition is then performed in acolumn-by-column manner and, according to the code, successive columnsare one microsecond apart in There is also incorporated in the addingbox a delay of exactly one microsecond between the input and the outputterminals. This delay causes a carry output impulse, resulting from theaddition of one column, to appear at the carry output terminal 225, andtherefore at the third input terminal 224, at exactly the same time asthe input impulse representations of the next column appear at the lirstand second input terminals 222 and 223. In addition, the one microseconddelay between the input and the other output terminal 226 causes, ineffect, a column shift of one column of the sum. This is necessary foradding that sum to the next partial product in the next adding box inthe chain.

The operation of the adding box is based on the fact that in adding twobinary numbers manifested in time coded impulses together, column bycolumn, only four possible conditions can be encountered by the addingbox, viz: (l) no input pulses, (2) a single input impulse, (3) twosimultaneous input impulses, and (4) three simultaneous input impulses.The manner in which the irst condition might arise is, of course,obvious. The second condition may arise upon the adding box receiving asingle impulse representing a binary l in the column being added in oneof the two numbers being added, or an impulse representing a binary lcarry over from the addition of the previous column. The third conditionmay arise upon the adding box receiving simultaneously a single inputimpulse representing a binary 1 in the column being added in one of thetwo numbers being added, and another irnpu-lse representing either abinary l in the column being added of the other number or a binary 1carry. The fourth' condition may arise upon the adding box receivingsimultaneourly two impulses representing a binary l in both. of thenumbers being added and a third impulse representing axbinary 1 carry.

The three input terminals 222, 223 and 224 of the adding box inaccordance with the present invention feed three coincidence tubes 227,228 and 229, which are preferably pentodes, such as Western Electric6AS6 tubes. The a'nodes of the three coincidence tubes 227, 228 and 229are connected through a resistor 230 andan inductor 231 to the +110volts supply line, while the cathodes are grounded. The screen grids ofthe three coincidence tubes are connected together and through aresistor 232 and an inductor 233 in parallel therewith to the +110 voltssupply line. The suppressor `and control grids of the three coincidencetubes are interconnected in a symmetrical pattern with the three inputterminals 222, 223 and 224. The first input terminal 222 is connected tothe control grid of the rst tube 227 and the suppressor grid of thesecond tube 228. The second input terminal 223 is connected to thecontrol grid of the second tube 228 and the suppressor grid of the thirdtube 229. The third input terminal 224 is connected to the suppressergrid of the rst tube 227 and the control grid of the third tube 229.Normally, these grids are biased by the voltage levels of the inputfeeds so that the three tubes 227, 228 and 229 arecompletely cut offwhen there are no impulses on any of the input terminals 222, 223 and224. The arrangement is such that a positive impulse appearing only onthe control. grid of a coincidence tube causes a high screen gridcurrent and results in a negative voltage impulse at the screeny grid. Apositive impulse only on the suppressor grid of a coincidence tube doesnot affect that tube at all. A positive impulse appearing simultaneouslyon both the control grid and the suppressor grid of a coincidence tuberesults in a negative voltage impulse at the anode as well as a negativevoltage impulse at the screen grid. When negative voltage impulsesappear at both the anode and the screen grid of one of the coincidencetubes, the reduction in the magnitude of the screen grid impulse whichtends to result from the simultaneous presence of the anode pulse isolfset by the fact that more than one ofthe coincidence tubes 227, 228and 229 is, under these conditions, providing a screen grid impulse.

The screen grid circuit for the three coincidence tubes 227, 228 and 229drives the control grid of another pentode 234, such as a WesternElectric 6AS6 tube, through an impulse inverter circuit. The anode ofthe pentode 234 is connected through a resistor 235 and an inductor 236to the +110 volts supply line. The cathode of the pentode 234 isgrounded and the screen grid is connected to the +110 volts supply line.The control grid of the pentode 234 is coupled through a condenser 238to the screen grids of the three coincidence tubes 227, 228 and 229. Thecontrol grid of the pentode 234 is also connected through a resistor 239to the -110 volts supply line and through a diode 240, preferably agermanium crystal diode, to the biasing voltage line B2, with the diodeoffering its lower impedance to current flow from the biasing line B2.The D.C. bias on line B2 may be supplied from a conventional D.C. sourceandy may have a valve in the order of minus six volts. This arrangementis such that the rest voltage of the control grid of the pentode 234 isthat of biasing B2 which is suiciently negative to maintain the pentodebelow cuto.

When a negative voltage impulse appears at the screen grid of one ormore of the three coincidence tubes 227, 228 and 229, the couplingcondenser 238, which had previously been charged to the voltagedifference between the +110 volts and the B2 biasing line, loses chargebecause the terminal thereof which is connected to the control grid ofthe pentode 234 isprevented by the. arrangement of.

diode 240 from going more negative than the voltage of biasing line B2.However, as the negative voltage impulse on the screen grid of acoincidence tube is terminated, the voltage thereof rises and because ofthe condenser coupling a positive impulse is passed through to Ithecontrol grid of the pentode 234. The upper limit of the positive voltageon the control grid of the pentode 234 under these conditions isdetermined by the ow of grid current through the pentode 234 when thegrid reaches approximately the voltage of the cathode. Following thepositive impulse, the control grid of the pentode 234 is caused toreturn to its rest voltage by the combination of an overshoot of thescreen grid circuit, and the action of the resistor 239 connected to thevolts supply line, which tends to lower the grid voltage to at least thelevel of biasing line B2.

The suppressor grid of the pentode 234 is connected through anotherdiode 241, also preferably a germanium crystal diode, and a condenser242 to the junction point between the inductor 231 and the resistor 230in the anode circuit for the three coincidence tubes 227, 228 and 229. Aresistor 243 is connected in parallel with the diode 241 which offersits lower impedance to current ow from the suppressor grid. The junctionbetween the diode 241 and the condenser 242 is connected to a junctionbetween a resistor 256 and another resistor 244 which are in series fromthe +110 volts line to the ground. Thus, the` suppressor grid isnormally held at a voltage slightly more positive thanA the cathode.

If the suppressor grid ofthe pentode 234 is at, or more positive than,the voltage of the cathode, the presence of a positive voltage impulseat the control grid of the pentode 234 resulting from the termination ofa negative voltage impulse at the screen grids of the coincidence tubes227, 228 and 229, causes the pentode 234 to become conductive and anegative voltage impulse to appear at its anode.

The anode of the pentode 234 is coupled through a pulse inverter andsynchronous delay circuit to the grid of a triode 245 connected in acathode follower circuit. This pulse inverting and synchronous delaycircuit is exactly like the one shown and described in connection witheach stage of the electronic commutator in Figs. 2e and 2f of theabove-identified parent application, which forms the subject matter of adivisional application, now Patent 2,903,579 issued September 8, 1959and entitled, Pulse Delay Apparatus, with the exception that theresistor for eliminating parasitic oscillations is placed in the gridcircuit instead of` in the anode circuit of the triode 245. Preferablythe triode 245 is one-half of a twin triode, such as a Western Electric2C5l tube. The operation'of the pulse inverting and delay circuit inaccordance with the present invention is substantially the same as thatin Figs. 2e and 2f of the above-identified parent application. Briefly,this impulse producing means or circuit tends to produce an output pulseperiodically but is effective actually to produce an output pulse onlyat a pulse period immediately following an application thereto of asignal.

In the pulse inverting and synchronous delay circuit of the presentinvention, the anode of the pentode 234 is connected through a couplingcondenser 246, a rst diode 247, and a resistor 248 to the grid of thetriode 245. The rst diode 247 ofers its lower impedance to current flowtoward the grid. The terminal of the coupling condenser 246 remote fromthe anode of. the

pentode 234 is connected through a second diode 249v to the biasingvoltage line B2 with the diode 249 offering its lower impedance tocurrent ow toward the biasing line B2. The same terminal of the couplingcondenser 246 is connected through a third diode 250 to the biasingVoltage line B1 with the third diode 253 offering its lower impedance tocurrent ilow away from the biasing line B1. Biasing line B1 may besupp-lied with. a constant D C. voltage in the order of -27 volts from aconventional D.C. voltage source (not. shown). The

same. terminal of. the coupling condenser 246 is also con-i nectedthrough a resistor 251 to the '110 volts supply line, the latter alsobeing connected through a load resistor 252 to the cathode of the triode245. The junction point between the rst diode 247 and the resistor 248is connected through a coupling condenser 253 to a synchronous voltageimpulse line S2. The same junction polnt is also connected through afourth diode 254 and a resistor 255 to a clamp voltage impulse line K2.The output terminal 226 for the adding box is connected to the cathodeof the triode 245 while the anode thereof is connected to the +100 voltssupply line. The i'lrst, second, third and fourth diodes 247, 249, 250and 254 are all preferably germanium crystal diodes.

A voltage impulse is supplied to the adding box over the synchronousimpulse line S2 once each microsecond. This is a positive, rectangular,low impedance, synchro nous voltage impulse which may be supplied from aknown pulse generator such as that described for instance in the abovementioned Patent 2,672,283, and particularly in connection with Figure2g of that patent. This synchronous impulse is arranged to beapproximately one third of a microsecond in duration. A negative voltageimpulse is supplied to the adding box over the clamp impulse line K2from the synchronizer once each microsecond as explained hereinafter,and coincides with the termination of the synchronous impulse on lineS2. This is a negative voltage impulse having a steep wave front whichmay be supplied from a known pulse generator such as that shown anddescribed in connection with Figure 2g of the above mentioned Patent2,672,283. This is a very narrow negative voltage impulse of relativelylarge amplitude which occurs precisely at the end of each synchronousimpulse on line S2. Between successive K2 negative impulses, the restpotential of the clamp line K2 is just a few volts above groundpotential.

Let it be assumed that the grid of triode 245 is at the potential ofline B1 with condenser 253 charged to the diterence between line B1 andthe normal voltage of synchronous line S2. Because of the connection ofthe -1l0 volts line through the resistor 251 to the junction between thecoupling condenser 246 and the first diode 247, that junction tends tobe highly negative but is limited to the voltage of biasing line B1 bythe third diode 250. The grid of triode 245 is also prevented frombecoming more negative than biasing -line B1 by the third and iirstdiodes 251i and 247. Now when a negative voltage impulse appears at theanode of the pentode 234, the coupling condenser 246 which has beenpreviously charged to the voltage diierence between the l-ll() volts andthe biasing line B1, is discharged. However, during this discharge theterminal of the condenser 246 remote from the anode of the pentode 234is maintained substantially at the voltage of line B1 because of itsconnection thereto through the third diode 250. As the negative anodeimpulse at the pentode 234 ends, a positive impulse is passed throughthe coupling condenser 246 and the first diode 247 to the grid of thetriode 245 and to condenser 253. The magnitude of this positive impulseis limited by the arrangement of the second diode 249, to the differencebetween the voltages of biasing lines B1 and B2. This positive impulsechanges the charge on the condenser 253 coupling the grid of the triode245 to the synchronous impulse line S2, so that even after the positiveimpulse is terminated, the grid remains at the voltage of biasing lineB2.

The purpose of the first diode 247 is to permit the voltage of theterminal of the coupling condenser 246 remote from the anode of thepentode 234 to return to the voltage level of line B1 without changingthe voltage of the grid of the triode 245. Such return of the voltage ofthe condenser terminal is eiected by an overshoot of the anode impulseof the pentode 234 and the action of the resistor 251 connecting theterminal to the -110 volts supply line.

It is then evident that while the pentode 234 remains non-conductive,the grid of triode 245 remains at the negative voltage level of biasingline B1. While the grid is at this level, the application of asynchronous impulse thereto does not produce a suflicient impulse outputof the triode 245 to actuate any of the tubes to be supplied therefrom.On the other hand, when the pentode 234 becomes conductive and thennon-conductive, a voltage pedestal of the level of line B2 isestablished on the grid of the triode 245. With the grid at the level ofline B2, a synchronous impulse produces an effective impulse at thetriode output. Since the pentode 234 becomes conductive as a result ofthe coincidence tube or tubes becoming non-conductive following receiptof an impulse, and the voltage pedestal at the grid of triode 245 isestablished as a result of the pentode 234 becoming noneconductive, itis apparent that the synchronous impulse producing the output impulse isthat synchronous impulse which occurs at the next time period after thetime period in which the input impulse to the adding box originallyoccurred. Thus, the output impulse occurs one microsecond after theinput impulse..

As the synchronous impulse ends, the negative clamping impulse having asteep wave front is supplied over line K2 causing the grid of the triode245 to be lowered to the voltage level of line B1. The fourth diode 254and the resistor 255 in series therewith serve to isolate the clampingsupply line K2. The constants of the load circuit of the pentode 234 areselected to provide the desired shape for the voltage pedestal.

It now appears that when a negative voltage impulse appears at thescreen grids of the three coincidence tubes 227, 228 and 229 and thesuppressor grid of the pentode 234 remains at or above the voltage ofits cathode, a positive Voltage impulse is delivered to the outputterminal 226 of the adding box exactly one microsecond after the inputimpulses which caused the screen grid impulse.

While the suppressor grid of the pentode 234 is normally slightlypositive with respect to its cathode, the presence of a negative impulseat the anodes of the three coincidence tubes 227, 228 and 229 causes thesuppressor grid to become more negative. As previously mentioned, such anegative anode impulse yat the three coincidence tubes results from thepresence of two or more simultaneous impulses on the three inputterminals. This negative impulse at the anodes of the coincidence tubesis transmitted to the suppressor grid of the pentode 234 through thecoupling condenser 242 and the diode 241. When the suppressor grid ofpentode 234 is negative, it prevents the anode of pentode 234 frombecoming conductive in response to a positive impulse on the control grrIt is to be noted that the negative impulse on the suppressor grid ofpentode 234 is obtained from the inductive portion, i.e., inductor 231,of the load of the three coincidence tubes. This arrangement is used toprevent undesirable changes in the average voltage of the suppressorgrid which would result if condenser 242 were connected directly to theanodes of the coincidence tubes. The positive impulses on the controlgrid of the pentode 234 resulting from a negative impulse at the screengrids of the coincidence tubes .is delayed somewhat since the positiveimpulse is the result of the termination rather than the initiation ofthe negative screen grid impulse at the coincidence tubes. However, byhaving the negative impulse on the suppressor grid of the pentode 234supplied directly by the anode circuit of the coincidence tubes and byhaving the voltage of the suppressor grid returned to its rest or normalvalue more slowly than the lower terminal of the coupling condenser 242because of the arrangement of the diode 241 land resistor 243, thesuppressor grid is maintained negative over a suiiicient interval toinsure blocking of the pentode 234 even though a positive impulse issupplied to the control grid. Thus, it is evident that when two or 7more impulses occur simultaneously on the input terminals 222, 223 and224, the anode of pentode 234 is maintained non-conductive.

In yadding a single column of two numbers in the binary system, a binary1 plus a binary (l, represented by a single impulse on one of the inputterminals `222, 223 and 224 of an adding box in accordance with thepresent invention, equals a binary 1, represented by a single impulseproduced at the output terminal 226 as a result of the screen gridimpulse at the coincidence tubes 227, 228 and 229 and the operation ofthe pentode 234 and triode 245 as previously described. However, abinary l plus another binary 1, as represented by two simultaneousimpulses on two of the input terminals 222, 223 and 224, equals a binarywith a binary 1 being carried over to the next column. Consequently,there should not be an impulse on the output terminal 226 in this lastexample, buta carry impulse must be provided. Now when two or more inputimpulses occur simultaneously, there is produced a negative impulse atthe anodes of the coincidence tubes 227, 22S and 229, as well as attheir screen grids. The anode impulse is effective as just described toblock the tendency of the screen grid impulse to produce an outputimpulse at the output terminal 226 to represent a binary l and theabsence of an impulse at the output terminal 226 then represents abinary 0. This same anode impulse is also employed to produce thenecessary 'carry impulse at the carry terminal 225.

The anodes of the three coincidence tubes 227, 228 and 229 are coupledto the grid of another triode 257 through another impulse producing orpulse inverting and synchronous delay circuit similar to that describedbetween the pentode 234 and the other triode 245. This pulse invertingand delay circuit comprises a condenser 258, a rst diode 259, and aresistor 260 connected in series between the anodes of the coincidencetubes 227, 228 and 229 and the grid or" the triode 257. There are alsoincluded a second diode 261 connecting the terminal of the condenser 25Sremote from the anodes of the coincidence tubes to the biasing voltageline B2, a third diode 262 coupling the same terminal to the biasingline B1, a resistor 263 connecting the same terminal to the -110 voltssupply line, a condenser' 264 coupling the grid of the triode 257 to thesynchronous impulse line S2 and la fourth diode 265 and a resistor 266connecting the grid to the clamp impulse line K2. The triode 257 may behalf of a twin triode of which the triode 245 is the other half. Theanode of the triode 257 is connected to the +110 volts supply line. Thecathode of the triode 257 is connected through a load resistor 267 tothe -110 volts supply line, and is also connected to the carry outputterminal 225.

The operation of this pulse inverting and synchronous delay circuitfeeding the triode 257 is exactly like that of the delay circuit feedingthe triode 245, as previously described. Therefore, when a negativeimpulse appears at the anodes of the coincidence tubes, a positiveimpulse appears exactly one microsecond later at the carry outputterminal 225 which is connected directly to the third input terminal224.

AIt now appears that when two input impulses occur simultaneously on twoof the input terminals producing a negative impulse at both the screengrids and the anodes of the coincidence tubes,an impulse is not providedat the output terminal 226 but an impulse is provided at the carryterminal 225, one microsecond later.

When an impulse occurs simultaneously on each of the three inputterminals 222, 223 and 224 of the adding box, an impulse should beproduced for proper `addition on both the output terminal 226 and thecarry terminal 225 inasmuch as a binary 1 plus a second binary l plus athird binary 1 equals a binary l with a carry of a binary 1 to the nextcolumn. 1t has already been pointed out that simultaneous impulses onthe three input terminals :causes anegative impulse atthescreen grids`and at the anodes of the coincidence tubes A227, 228 and 229. Thisproducesran impulse at the carry output terminal 225 one microsecondlater but the tendency of the screen grid impulse to produce an outputimpulse at the output terminal 4226 through the pentode 234 is blocked.To provide such an output impulse under these conditions, a novel triplecoincidence circuit is provided.

The triple coincidence circuit incorporates three diodes 268, 269 and270, preferably germanium crystal diodes, connected, respectively,between the three input terminals 222, 223 and 224 and a common line 271with the diodes offering their lower impedance to current ow 4toward theinput terminals. The common line 271 of the three diodes 26S, 269, 276is connected through a resistor 272 to the volts supply line. It is alsoconnected to the controlling member or control grid of a work devicepreferably comprising another pentode 273, such as a Western Electric6AK5 tube. The anode of the second pentode 273 is connected to the anodeof the rst pentode 234 and therefore is connected through the resistor235 and the parallel connected condenser 237 and inductor 236 to the+1110 volts supply line, as well as to the grid of thettriode 245through the pulse inverting and synchronous delay circuit therebetween.The cathode of the second pentode 273 is connected to the ground and tothe suppressor grid, and the screen grid is connected to thel-l- 1 10volts supply line.

By the arrangement described, the common line 271 of the three diodes268, 269 and 276 can be but very little more positive than the voltageof the most negative of the input terminals 222, 223 and 224. in otherwords, for the common line 271 to have a positive impulse, it isnecessary that all three input terminals 222, 223 and 224 have apositive impulse thereon at the same time. When this occurs, the secondpentode 273 becomes conductive and passes an impulse to the triode 245to produce in turn an impulse at the output terminal 226 one microsecondafter the input pulses. It is then obvious that when input impulses areapplied simultaneously to the three input terminals, the second pentode273 acts on the lirst triode 245 to produce an output impulse atterminal 226 while the anode impulse of the coincidence tubes 227, 228and 229 produces a carry impulse at terminal 225 and blocks the rstpentode 234 which is responsive to screen grid impulse of thecoincidence tubes.

From the foregoing description of an adding box as shown in the singlegure of the drawing, it is evident that a single input impulse producesa single output im pulse at terminal 226; two simultaneous inputimpulses produce only a carry impulse; and three simultaneous inputimpulses produce an output impulse at terminal 226 and a carry impulse.The output and carry impulses are delayed exactly one microsecond in allcases which is to be remembered in interpreting the time coded impulsesrepresenting the sum `of the numbers added by the adding box.

While in the description of the fundamental novel teatures of myinvention as applied to a preferred ernbodiment and as illustrated inthe drawing, reference has been made to tubes of specic types, i-t willbe understood that other tubes of suitable characteristics may beemployed instead. -It will also be understood that various otheromissions, substitutions and changes in the form. and details of thedevices illustrated and in its operation may be made by those skilled inthe art without departing yfrom the spirit of the invention. It is theintention, therefore, to be limited only as indicated by the scope ofthe following claims.

What is claimed is:

1. In an electronic adding circuit, the combination comprising. aplurality of input lines adapted to have input voltage impulses appliedthereto individually, a pair of load circuits connected from a positiveto a negative voltage supply point, electronic tube means in said loadcircuits 4for controlling current therethrough and connected to saidinput lines to be responsive to an input impulse on any one of saidlines to cause a current impulse in the first of said load circuits andresponsive to two simultaneous impulses on any two lines to cause acurrent impulse in the second load circuit, the first load circuitincluding a resistor connected from said positive point to said -tubemeans and the second load circuit including an inductor and a resistorconnected in series in the order named from said positive point to thetube means, a pair of pulse circuits for producing output pulsesresponsive to individual signal impulses, a control tube coupled to thefirst of said pulse circuits to supply a signal impulse thereto upon acurrent impulse through the control tube, said tube having two gridscontrolling the conductivity thereof, a voltage impulse invertingcircuit connecting one of said grids to the first load circuitintermediate the resistor therein and the tube means and effective tomaintain said control tube normally nonconductive but responsive to thedecay of a voltage impulse appearing at its point of connection to thefirst load circuit to apply a voltage impulse of opposite polarity tosaid one grid to cause a current impulse through the control tube, saidsecond pulse circuit being coupled to said second load circuitintermediate the resistor thereof and the tube means to receive a signalimpulse upon the occurrence of a current impulse through the second loadcircuit, a rectifier and a resistor connected in parallel with eachother and in series with a coupling condenser in the order named fromthe other grid to said second load circuit intermediate the resistor andinductor therein, and another resistor connecting a point intermediatethe rectifier and condenser to a source of Voltage normally maintainingsaid other grid at a voltage permitting said inverted impulse at saidone grid to render the control tube conductive, whereby a currentimpulse through said second load circuit causes a voltage impulse on theother grid to prevent a simultaneous current impulse through said firstcircuit for causing the control tube to become conductive.

2. Apparatus according to claim l in which the impulse inverting circuitcomprises resistive means connecting said one grid to a source ofvoltage more negative than said positive point, a rectifier connectingsaid one grid to another source of voltage of a value intermediate saidfirst source and said positive point, said rectifier offering its lowerimpedance to current flow toward said one grid, and a condenserconnected between said one grid and the first load circuit intermediatethe resistor therein and the tube means.

3. An adding circuit comprising three input lines adapted to have inputvoltage impulses applied thereto individually; three electronic tubes,each having an anode, a cathode and at least three grids, with one ofthe grids of one tube connected to the corresponding grid of both of theother tubes and the two remaining grids of each tube `connected to twodifferent ones of said input lines with corresponding ones of said tworemaining grids being connected to different ones of the input lines;means connecting all of said anodes together and all of said cathodestogether in a common main load circuit; means connecting saidinterconnected one grids and cathodes in a common auxiliary loadcircuit, each of said tubes being normally non-conductive and responsiveto an input impulse on one of the lines to which its grids are connectedto cause a current impulse in said auxiliary load circuit and responsiveto simultaneous input impulses on both of the lines to which its gridsare connected to cause a current impulse in both said main and auxiliaryload circuits, rst and second output terminals; an impulse producingcircuit connected to each output terminal and effective to provide anoutput impulse at a preselected instant following an application theretoof an initiating signal; coupling means connecting said auxiliary loadcircuit to the first of said impulse producing circuits and responsiveto a current impulse through the former to supply a signal to thelatter; said main load circuit being coupled to the second impulseproducing circuit to supply a signal thereto upon a current impulsethrough the main `load circuit; means connecting said main load circuitto said coupling means and responsive to a current impulse in the mainload circuit to prevent the supply of a signal from said auxiliary loadcircuit to said first impulse producing circuit; and coincidence meansconnected to said input lines and responsive to simultaneous inputimpulses on all of said lines to supply a signal to said first impulseproducing circuit.

4. An adding circuit comprising three input lines, two of which areadapted to have applied thereto individually, at spaced index points intime, coded voltage input impulses representing in the binary system twonumbers to be added with successive index points corresponding tosuccessive increasing orders; an output terminal; a carry terminalconnected to the third input line to transfer thereto impulses appearingat the carry terminal; three electronic tubes, each having an anode, acathode and at least three grids, with one of the grids of one tubeconnected to the corresponding grid of both of the other tubes and thetwo remaining grids of each tube connected to two different ones of saidinput lines with corresponding ones of said two remaining grids beingconnected to different ones of the input lines; means connecting all ofsaid anodes together and all of said cathodes together in a common mainload circuit; means connecting said interconnected one grids andcathodes in a common auxiliary load circuit, each of said tubes beingnormally non-conductive and responsive to an input impulse on one of thelines to which its grids are connected to cause a current impulse insaid auxiliary load circuit and responsive to simultaneous inputimpulses on both of the lines to which its grids are connected to causea current impulse in both said main and auxiliary load circuits; firstimpulsing means connected to the output terminal and actuatable inresponse to a current impulse in said auxiliary load circuit to providean impulse at the output terminal at the next index point time; secondimpulsing means connected to the carry terminal and actuatable inresponse to a current impulse in said main load circuit to provide animpulse at the carry terminal at the next index point time; meansresponsive to a current impulse in said main load circuit to preventactuation of the first impulsing means in response to a simultaneouscurrent impulse in the auxiliary load circuit; and coincidence meansconnected to said input lines and responsive to simultaneous impulses onall three lines to actuate the first impulsing means to produce animpulse at the output terminal at the next index point time.

5. An adding circuit comprising three input lines, two of which areadapted to have applied thereto individually, at spaced index points intime, coded voltage input impulses representing in the binary system twonumbers to be added with successive index points corresponding tosuccessive increasing orders; a pair of electronic tubes havingindividual load circuits; an output terminal connected to the loadcircuit of the first tube; a carry terminal connected to the second tubeload circuit and also to the third input line to transfer theretoimpulses appearing `at the carry terminal; control means for each ofsaid tubes including synchronizing means tending to cause the tube tosupply an output impulse to the corresponding terminal at each indexpoint time but actually effective to cause such output impulse only whenconditioned subsequent to the preceding index point time; meansconnected to said input lines and responsive to an impulse on any one ofsaid lines to condition the first tube control means subsequentlythereto but prior to the next index point time and responsive tosimultaneous impulses on any two of said lines to condition only thesecond 11 tube control means subsequently thereto but prior to the nextindex point time; and coincidence means connected to said input linesand responsive to simultaneous impulses on all three lines t'o conditionthe first tube control means subsequently thereto but prior to the nextindex point time.

6. An adding circuit comprising at least three input lines adapted tohave input voltage implulses applied thereto individually, first andsecond output terminals, an impulse producing circuit connected to eachoutput terminal and effective to provide an ontput impulse at apreselected instant following an application thereto of a signal, meansconnected to said input lines and responsive to an input impulse on anyone thereof to apply a signal only to the first of the impulse producingcircuits and responsive to simultaneous input impulses on any two inputlines to apply a signal only to the second of the impulse producingcircuits, and coincidence circuit means connected to said input linesand responsive to simultaneous input impulses on all of said input linesto apply -a signal to the first impulse producing circuit, saidcoincidence circuit means comprising a device connected to said firstimpulse producing circuit and having a control member, means connectedto said control member tending to cause it to be at a predeterminedvoltage, said device providing a signal to said first impulse producingcircuit only upon said member changing from said predetermined voltage,`and a rectifier for each input line connected between that line andsaid member with all of the rectifiers arranged to conduct current inthe same direction relative to said member.

7. An adding circuit comprising at least three input lines adapted to benormally at a first voltage level and to have input voltage impulsesapplied thereto individually, means connected to said input lines andresponsive to an input impulse on any one of said lines to provide acorresponding impulse at a first point and responsive to simultaneousinput impulses on any two input lines to provide a corresponding impulseat a second point, first and second output terminals, an impulseproducing circuit connected to each output terminal and effective toprovide an output impulse at a preselected instant following anapplication thereto of a signal impulse, said second point being coupledto the second impulse producing circuit whereby a signal impulse isapplied to the latter upon the appearance of an impulse at the former,an electronic tube connected in a load circuit to effect the applicationof a signal impulse to the first impulse producing circuit upon acurrent impulse in said load circuit, first control means for said tubenormally maintaining it in one condition with respect to conductivity,said first control means being connected to said first point andresponsive to an impulse thereon to change momentarily the condition ofsaid tube to cause a current impulse in said load circuit, secondcontrol means for said tube connected to said second point andresponsive to an impulse thereon to prevent a simultaneous impulse atthe first point from effecting a change in the condition of the tube,and coincidence circuit means connected to said input lines andresponsive to simultaneous input impulses on all of said lines to supplya signal impulse to said first impulse producing circuit, saidcoincidence circuit means comprising a second electronic tube, an outputcircuit for said second tube connected to said first impulse producingcircuit, said second tube having an electrode controlling output currenttherethrough in accordance with the voltage of said electrode, animpedance member connecting the electrode to a source of second voltageydifferent from said first voltage and with the same polarity relativethereto as said input impulse, whereby the electrode tends to be at saidsecond voltage, and a rectifier for each input line connected betweenthat line and said electrode and arranged to conduct current toward thenormally more negative one of` said' second voltage and that line,whereby the electrode is maintained at said first voltage except whenall of said input lines have an impulse thereon.

8. An adding circuit having a plurality of input terminals, comprising:a multi-electrode electron discharge device associated with each saidterminal, means comprising first electrodes of each of said devices fordeveloping a first output signal when input signals are applied to twoor more of said terminals, means comprising second electrodes of each ofsaid devices for developing a second output signal when input signalsare applied to one or more of said terminals, means for developing athird output signal when input signals are applied to three of saidterminals, means for utilizing said first output signal to control saidsecond output signal, and means for combining said controlled outputsignal and said third output signal to provide an adding circuit outputsignal.

9. An adding circuit having a plurality of input terminals, comprising:a multi-electrode electron discharge device associated with each saidterminal; means comprising first electrodes of each of said devices fordeveloping a first output signal when input signals are applied to twoor more of said terminals; means comprising second electrodes of each ofsaid devices for developing a second output signal when input signalsare appiied to ione or more of said terminals; means for developing athird output signal when input signals are applied to all of saidterminals, said means comprising plural rectifier elements; means forutilizing said first output signal to control said second output signal;and means for combining said controlled output signal and said thirdoutput signal to provide au adding circuit output signal.

10. An adding circuit having a plurality of input terminals, comprising:a multi-electrode electron discharge device associated with each saidterminal; means comprising first electrodes of each of said devices fordeveloping a first output signal when input signals are applied to twoor more of said terminals; means coniprising second electrodes of eachof said devices for developing a second output signal when input signalsare applied to one or more of said terminals; means for developing athird output signal when input signals are applied to all of saidterminals; means for utilizing said first output signal to control saidsecond output signal, said means comprising an electron discharge devicehaving a control electrode and rectifier means for applying said firstoutput signal to said last-mentioned control electrode; and means forcombining said controlled output signal and said third output signal toprovide an adding circuit output signal.

1l. An adding circuit having a plurality of input terminals, comprising:a multi-electrode electron discharge device associated with each saidterminal, means comprising first electrodes of each of said devices fordeveloping a first output signal when input signals are applied to twoor more of said terminals, means comprising second electrodes of each ofsaid devices for developing a second output signal when input signalsare applied to one or more of said terminals, means comprising a firstelectron discharge device for developing a third output signal wheninput signals are applied to all of said terminals, means comprising asecond electron discharge device for utilizing said first output signalto control said second output signal, and means for combining saidcontrolled output signal and said third output signal to provide anadding circuit output signal, said combining means comprising a loadimpedance common to said first and second electron discharge devices.

l2. An adding circuit comprising three input lines, two of which areadapted to have applied thereto individually, at spaced index points intime, coded voltage input impulses representing in the binary system twonumbers to be added with successive index points corresponding tosuccessive increasing orders; an output' terminal; a carry terminalconnected to the third input line to transfer thereto impulses appearingat the carry terminal; a first impulse producing circuit connected tothe output terminal; a second impulse producing circuit connected to thecarry terminal, each of said impulse producing circuits being effectiveto provide an impulse at the corresponding terminal at the next indexpoint time following an application thereto of a signal; means connectedto said input lines and responsive to an impulse on any one thereof toapply a signal to the rst impulse producing circuit and responsive tosimultaneous` impulses on any two input lines to apply a signal only tothe second impulse producing circuit; and coincidence circuit meansconnected to said input lines and responsive to simultaneous impulses ouall three lines to apply a signal to the first impulse producingcircuit.

13. An adding circuit comprising three input lines, two of which areadapted to have applied thereto individually, at spaced index points intime, coded voltage input impulses representing in the binary system twonumbers to be added with successive index points corresponding tosuccessive increasing orders; an output terminal; a carry terminalconnected to the third input line to transfer thereto impulses appearingat the carry terminal; means connected to said input lines andresponsive to an impulse on any one of said lines to provide an impulseat a first circuit point and responsive to simultaneous impulses on anytwo of said lines to provide an impulse at a second circuit point; firstimpulse producing means actuatable in response to an impulse at saidfirst circuit point to produce an impulse at the output terminal at thenext index point time; means responsive to an impulse at said secondcircuit point to prevent actuation of said first impulse producing meansin response to a simultaneous impulse at said first circuit point;second impulse producing means responsive to an impulse at said secondcircuit point to produce an impulse at the carry terminal at the nextindex point time; and coincidence circuit means connected to said inputlines and responsive to simultaneous impulses on all three lines toactuate said first impuse producing means to produce an impulse at theoutput terminal at the next index point time.

14. A binary full adder including sum circuit means for providing abinary sum output at a first terminal, carry circuit means for providinga binary carry output at a second terminal, input means for receivingthree binary inputs to be added in binary fashion, an OR circuitconnected to said input means and to said sum circuit means to exhibitmanifestations at said rst terminal corresponding to receipt of onesignal only on said inputs, an inhibiting circuit cooperating with saidOR circuit and preventing a manifestation at said first terminal uponreceipt of two inputs only, means cooperating with said OR circuit toproduce a manifestation on said second terminal upon receipt of at leasttwo inputs, and means comprising a separate coincidence circuitconnected to said sum circuit means for producing a manifestation onsaid first termina-l upon receipt of three inputs.

15. An adding circuit comprising at least three input lines adapted tohave input voltage impulses applied thereto individually, first andsecond output terminals, an inpulse producing circuit connected to eachoutput terminal and effective to provide an output impulse at apreselected instant following an application thereto of a signal, meansconnected to said input lines and responsive to an input impulse on anyone thereof to apply a signal only to the first of the impulse producingcircuits and responsive to simultaneous input impulses on any two inputlines to apply a signal only to the second of the impulse producingcircuits, and coincidence circuit means connected to said input linesand responsive to simultaneous input impulses on all of said input linesto apply a signal to the first impulse producing circuit.

16. An adding circuit comprising at least three input lines adapted tohave input voltage impulses applied thereto individually, meansconnected to said input lines and responsive to an input impulse on anyone of said lines to provide a corresponding impulse at a first pointand responsive to simultaneous input impulses on any two input lines lto`provide a corresponding impulse at a second point, first and secondoutput terminals, an impulse producing circuit connected to each outputterminal and effective to provide an output impulse at a preselectedinstant following an application thereto of a signal impulse, couplingmeans connecting said first point to the first of said impulse producingcircuits and responsive to an impulse at the former to apply a signalimpulse to the latter, said second point being coupled to the secondimpulse producing circuit whereby a signal impulse is applied to the`latter upon the appearance of an impulse at the former, means connectedto said coupling means and responsive to an impulse at said second pointto prevent the application of a signal impulse to the first impulseproducing circuit by reason of a simultaneous impulse at said firstpoint, and coincidence circuit means connected to said input lines andresponsive to simultaneous input impulses on yall of said lines tosupply a signal impulse to said first impulse producing circuit.

17. An adding circuit comprising `at least three input lines adapted tohave input voltage impulses applied thereto individually, meansconnected to said input lines and responsive to an input impulse on anyone of said lines to provide a corresponding impulse `at a iirst pointand responsive to simultaneous input impulses on any two input lines toprovide a corresponding impulse at a second point, first and secondoutput terminals, an impulse producing circuit connected to each outputterminal and effective to provide an output impulse at a preselectedinstant following an application thereto of a signal impulse, saidsecond point being coupled to the second impulse producing circuitwhereby a signal impulse is applied to the latter upon the :appearanceof an impulse at the former, an electronic tube connected in a loadcircuit to effect the application of a signal impulse to the firstimpulse producing circuit upon .a current impulse in said load circuit,control means for said tube connected to said first and second pointsand responsive to an impulse at the first point to cause a currentimpulse in said load circuit and responsive to an impulse at the secondpoin-t to prevent a current impulse in said load circuit by reason of asimultaneous first point impulse, and coincidence circuit meansconnected to said input lines and responsive to simultaneous inputimpulses on all of said lines to supply a signal impulse to said iirstimpulse producing circuit.

18. An adding circuit comprising at least three input lines 'adapted tohave input voltage impulses applied thereto individually, meansconnected to said input lines and responsive to an input impulse on anyone of said lines to provide a corresponding impulse at a first pointand responsive to simultaneous input impulses on any two input lines toprovi-de a corresponding impulse at a second point, first and secondoutput terminals, an impulse producing circuit connected to each outputterminal and effective to provide an output impulse at a preselectedinstant following an application thereto of a signal impulse, saidsecond point being coupled to the second impulse producing circuitwhereby a signal impulse is applied to the latter upon the .appearanceof an impulse at the former, an electronic tube connected in a loaidcircuit to effect the application of a signal impulse to the firstimpulse producing circuit upon a current irnpulse in said load circuit,first control means for said tube normally maintaining it in onecondition with respect to conductivity, said first control means beingconnected to said first point and responsive to an impulse thereon tochange momentarily the condition of said tube to cause a current impulsein said load circuit, second control means for-said tube connected tosaid second ypoint and responsive to an impulse thereon to prevent asimultaneous irnpulse at the iii-st point from eiiecting a change in thecondition of the tube, and coincidence circuit means connected to saidinput lines and responsive to simultaneous input impulses on all oi saidlines to supply a signal impulse to said first impulse producingcircuit.

19. An adding circuit having a plurality of input terminals, comprising:means for developing a iirst output signal when input signals areapplied to two or more of said terminals, means Ifor developing a secondoutput signal when input signals are applied to one or more of saidterminals, means for developing a third output 4signal when inputsignals are applied to all of said terminals, means for utilizing saidtirst output signal to control said second output signal, and meanscomprising a pulse circuit for combining said controlled second outputsignal and said third output signal to provide an adding circuit outputsignal pulse.

20. An adding 4circuit having a plurality of input terminals,comprising: electron discharge means for developing a rst output signalat a iirst circuit point when input signals are applied to two or moreof said terminals and for `developing a second output signal at a secondcircuit point when input signals are applied to one or more of saidterminals, means for developing a third output signal at a third circuitpoint when input signals are applied to all of said terminals, meansconnected for utilizing said ilrst output signal to control said secondoutput signal, and means connected for combining said controlled secondoutput signal and said third output signal to provide an adding circuitoutput signal.

2l. An adding circuit having a plurality of input terminals, comprising:a plurality of electron discharge devices for developing a first outputsignal when input signals are applied to two or more of said terminalsand for developing a second output signal when input signals are appliedto one or more of said terminals; means for developing a third outputsignal when input signals are applied to all of said terminals, saidmeans comprising rectifier elements; means for utilizing said firstoutput signal to control said second output signal, said meanscomprising an electron discharge device; and means for combining saidcontrolled second output signal and said third output signal to providean adding circuit output signal.

22. A circuit for effecting binary addition of three input signalscomprising three input lines normally maintained at a -rst potential andarranged to supply pulses to be added at a second potential, separatemulti-electrode electron devices respectively having control electrodesconnected to said input lines; each of said devices having a suppressionelectrode connected to one of said input lines which is different fromthe input line to which its control electrode is connected, each of saiddevices having a main output electrode connected to a common maincircuit and an auxiliary output electrode connected to a commonauxiliary circuit; each of said Idevices providing an output at itsauxiliary electrode to said auxiliary circuit upon the application of aninput pulse to its control electrode; each of said devices providing anoutput at its main output electrode to said main circuit upon theconcurrent application of input pulses to its control and suppressionelectrodes; a carry output device connected to said main circuit toprovide a carryoutput in response thereto; a sum output device connectedto said auxiliary circuit to provide a sum output in response thereto;an inhibit device connected between said auxiliary circuit and said sumoutput device and connected to receive signals from said main outputcircuit to inhibit the operation of said sum device in response thereto;and a coincidence circuit connected for operation in response toconcurrent input signals on all three of said input lines; saidcoincidence circuit being connected to provide for operation of said sumoutput device independent of Lsaid inhibit circuit.

23. An adding circuit for effecting binary addition of a plurality ofelectrical input signals comprising a plurality of input lines normallymaintained at a first potential value and arranged to have impressedthereon electrical pulses of a second potential value at predeterminedtime intervals for which addition is to take place; a multi-electrodeelectron device for each of said input lines, said devices each having acontrol electrode; said control electrodes being respectively connectedto said input lines; each of said devices having a suppression electrodeconnected to one of said input lines Whichis different 4from the inputline to which its control electrode is connected; each of said deviceshaving a main output electrode connected in common in a main circuit;each of said devices having an auxiliary outputrelectrode connected incommon in an auxiliary circuit; each of said devices being independentlyoperative to provide an output at its auxiliary output electrode forsaid auxiliary circuit upon the application of an input pulse `toitscontrol electrode irrespective of the condition of its suppressionelectrode; each of said devices being operative to provide an output atits main output electrode for said Amain circuit only upon theconcurrent application of input pulses to both its control and.suppression electrodes; a carry output device connected to said maincircuit to provide a carry output in response thereto; a sum outputdevice connected to said auxiliary circuit to provide a sum output inresponse thereto; an inhibit device connected between said auxiliarycircuit and said sum output ydevice and connected to receive signalsfrom .said main output circuit and operative to inhibit the operation ofsaid sum device upon the concurrent presence of signals from said mainand auxiliary circuits.

24. An adding circuit for effecting binary addition of three electricalinput signals comprising rst, second and third input lines normallymaintained at a first potential value and arranged to have impressedthereon electrical pulses of a second potential value at predeterminedtime intervals for which addition is to take place; first, second andthird multi-electrode electron devices each having a control electrode;said control electrodes being respectively connected to said first,second and third input lines;

r each of said devices having a suppression electrode; said suppressionelectrodes of said first, second and third devices being respectivelyconnected in the order. named t0 said third, rst and second input lines;each of said devices having a main output electrode connected in commonwith the other main output electrodes in a main circuit; each of saiddevices having an auxiliary output electrode connected in common withthe other auxiliary output electrodes in an auxiliary circuit; each ofsaid devices being independently operative to provide an output at itsauxiliary output electrode for said auxiliary circuit upon theapplication of an input pulse to its control electrode irrespective ofthe condition of its suppression electrode; each of said devices beingoperative to provide an output at its main output electrode for saidmain circuit only upon the concurrent application of input pulses toboth its control and suppression electrodes; a carry output deviceconnected to said main circuit to provide a carry output in responsethereto; a sum output device connected to said auxiliary circuit toprovide a sum output in response thereto; an inhibit device connectedbetween said auxiliary circuit and said sum output device and connectedto receive signals from said main output circuit and operative toinhibit the operation of said sum device upon the concurrent presence ofsignals from said main and auxiliary circuits; and a separatecoincidence circuit connected for operation in response to concurrentinput signals on all three of said input lines; said separatecoincidence circuit being connected to provide for operation of said sumoutput device independent of said inhibit circuit.

i7 i8 References Cited n the le of this patent 30, 1946). DeclassifedFeb. 13, 1947; pps. 1-1--11 to 1-l-14A; Figs. PY--OIOL 103, 104 and 177.UNITED STATES PATENTS Burks, A. W.: Electronic Computing Circuits of the10 the Edvac (Nov. 1, 1949), vol. II.

261696'5 Hppner NO'V' 4 1952 Engineering Research Associates, Inc., HighSpeed OTHER REFERENCES Computing Devices (July '28, 1950.), Pps. 276 to287. RCA Research Labs, neurone Ami-Aircraft Fire Tung Chang Chen: DwdeCommence and Mlxmg Circuits in Digital Computers, Proceedings of the IRECont-rol Predictor (April 14, 1942), pps. 72-73, Flg. 3.21. y y

Moore School of Electrical Engineering, Progress Re- 15 (May 1950) pages511 to 514 port #2 on the Edvac; University of Pennsylvania (June

